The present invention relates to the testing of connections between modules mounted on cards and more particularly to circuitry in the modules to provide simple testing of such connections.
Before modules are mounted on a card, the modules are each thoroughly tested and the wiring of the card is tested. The faults introduced by the assemblying of the modules on the card generally stem from defective connections to the pins of the modules which do not destroy the internal circuits on the modules. Therefore what really needs to be tested after the assembly of the circuits on the cards is the connections between the modules and the card. However in the past the layout of the modules has been such that this test can not be accomplished without taking into account the already tested circuitry on the module. Since this circuitry is rich in interconnections, generating tests for defective pin connections becomes an enormous task. Speaking more specifically, when the card I/O pins are the only accessible points for testing the test generation process must deal with the whole card full of logic circuits, that is, all the logic circuits on each of the modules mounted on the card. The fact that the fault sites are only at the module boundary, that is, at the pins of the module, does not make the job any easier. Even when the module pins are observable at the card testing one still has to find test inputs that will deliver sensitizing logic values to the module inputs.
In co-pending application Ser. No. 929,480 filed July 31, 1978, and entitled Chip Test Circuitry for Module Final Test a testing method and apparatus is described which could be used to test the connections between the modules and the cards using circuits on the modules in combination with mechanical probing of the cards.